1:30 pm - 6:00 pm, Monday, October 3, 2011
Koç University, Founders' Hall (Note new location!)
- Brief Introduction: A Principled Approach to Novel
Multi-Core Architecture and Programming Language Design
Dr. Serdar Taşıran
Department of Computer Engineering, Koç University
- Microsoft Research Connections in Europe, Middle
East, and Africa
Dr. Fabrizio Gagliardi
Director, Microsoft Research Connections, Europe, Middle East and Africa
Chair, Association for Computing Machinery (ACM) Europe Council
- Transactional Memory: A Promising Technology for
Prof. Dr. Osman Unsal
Senior Researcher, Barcelona Supercomputing Center - Microsoft Research Center
- Safe, Fast, Flexible: Revisiting
Architecture Support for Programming Language Runtime Systems
Dr. Tim Harris
Senior Researcher, Microsoft Research, Cambridge, UK
TALK ABSTRACTS and SPEAKER BIOGRAPHIES
The speaker will review current activities of Microsoft Research Connections in Europe, Middle East and Africa with special focus on the three joint institutes established in France with INRIA, in Italy with University of Trento and in Spain with University Politecnica of Catalonia.
Dr. Fabrizio Gagliardi is the Director of Europe, Middle East and Africa Director for Microsoft Research Connections (formerly External Research) at Microsoft Research. He has been in his present position since July 2008. In this position leading an EMEA team responsible for MSR Connections in EMEA. Based in Geneva with main office at the MSR research centre in Cambridge UK.
As part of this job supporting and contributing to MSR Cloud computing strategy in Europe, including the incubation of a major EU project (www.venus-c.eu), and with 3 direct engagements with major national funding agencies (EPSRC in the UK, INRIA in France and HLRS in Germany). Responsible for the strategic planning of the Cloud Computing team at EMIC in Germany.
He joined Microsoft in November 2005, when after the last EGEE conference in his home town of Pisa, Fabrizio Gagliardi took responsibility for the company Technical Computing Initiative in Europe, Middle East, Africa and Latin America. Before then and starting at the end of the 90 he was among the pioneers in developing and introducing Grid computing in Europe with early collaboration with Ian Foster and Carl Kesselman in the US, this led to projects like EU-DataGrid and EGEE, of which he was Principal Investigator and Director from 2000 till 2005. In 2004-2005 while still Director of EGEE (www.eu-egee.org) he contributed to the incubation and launch of more than 10 other Grid EU projects all inspired and supported by the EU EGEE flag-ship.
Dr. Gagliardi's appointments include the following:
In 1985-1987 he was advisor to the Director
of the Electra Synchrotron in Trieste Italy.
From 1985 till 2005 he was scientific advisor to the Director of the Scuola Normale in Pisa, one of the most prestigious universities in Italy.
From 2000 till 2005, advisor to the President of the Italian National Academy.
Since 1995, member of the scientific advisory board to Trento local government agency, FBK (http://www.fbk.eu/) .
Member of the Board of Directors of CoSBi (www.cosbi.eu) since 2008.
Member of the Board of Directors of INRIA-MSR joint institute (http://www.msr-inria.inria.fr/).
Director of the joint MSR institute on parallel computing at the Barcelona Supercomputing Centre (http://www.bscmsrc.eu/ ).
Since 2009 he is the chair of the ACM European Council ( http://europe.acm.org/) and also sits in the ACM Distinguished Speakers Programme International Committee.
Having recently surpassed the Petascale barrier, supercomputers designers and users are now facing the next challenge. A thousand fold performance increase that if the improvement rate of the last decades continues will be reached around 2018. Being power the main constraint and facing many hardware challenges, software is probably the biggest one. Worldwide and cooperative initiatives are being started to perform research facing such objective. The Barcelona Supercomputing Center is involved in such initiatives and carries out the MareIncognito research project aiming at developing some of the technologies that we consider will be of key relevance on the way to Exascale. The talk will briefly discuss relevant issues, foreseen architectures and software approaches that will have to be developed in order to successfully install and operate such machines.
Professor Mateo Valero, born in 1952, obtained his Telecommunication Engineering Degree from the Technical University of Madrid (UPM) in 1974 and his Ph.D. in Telecommunications from the Technical University of Catalonia (UPC) in 1980. He has been teaching at UPC since 1974; since 1983 he has been a full professor at the Computer Architecture Department. He has been Chair of the Computer Architecture Department and the Dean of the Computer Engineering School.
His research is in the area of computer architecture, with special emphasis on high performance computers: processor organization, memory hierarchy, systolic array processors, interconnection networks, numerical algorithms, compilers and performance evaluation. Since May 2004, he has been the director of the Barcelona Supercomputing Center (www.bsc.es), the National Center of Supercomputing in Spain. Professor Valero has co-authored over 500 publications: over 300 in Conferences and the rest in Journals and Books Chapters. He has been an associate editor of the IEEE Transactions on Parallel and Distributed Systems the IEEE Micro Journal and the IEEE Computer Architectura Letters, the Journal of Parallel Programming Languages, and the editor of several special issues of the IEEE Transactions on Computers and Computer Magazine. Prof. Valero has been honoured with several awards. Among them, the Eckert-Mauchly Award, the most important award in the world to recognize research in the field of computer architecture by the IEEE by the IEEE and the ACM. He is a Fellow of the IEEE, Fellow of the ACM and an Intel Distinguished Research Fellow.
These days everyone wants a "supercomputer" in their pocket. However, power-density limitations impedes the ability of such devices to deliver the expected speed and functionalities. This power wall represents a serious issue that vendors are addressing through the introduction of multi-core processors, which are more power-efficient than complex single-core chips. However, one key issue has not been addressed yet: writing software for these multi-core platforms (parallel programming) requires specialized skills. Transactional Memory (TM) is a new programming paradigm that simplifies parallel programming. TM support spans across the complete computer stack from applications down to hardware, encompassing language extensions, compilers, operating systems, runtimes, and processors. BSC- Microsoft Research Centre has been involved in TM research at each component of the stack, and this talk will introduce these contributions. We will also briefly introduce the work done in the European Union 7th Framework research project on TM, VELOX, which is coordinated by the Centre.
Osman Unsal is co-leader of the Architectural Support for Programming Models group at the Barcelona Supercomputing Center. Dr. Unsal is also a member of the Management Board of the BSC-Microsoft Research Centre. His current research interests include computer architecture, reliability, and ensuring programmer productivity. He holds BS, MS, and PhD degrees in electrical and computer engineering from Istanbul Technical University, Brown University, and University of Massachusetts, Amherst, respectively.
Modern safe programming languages rely on extensive software runtime systems that provide facilities such as distributing work across parallel processors, reclaiming storage space no longer needed by a program, or sandboxing a program's execution so that it does not interfere with the rest of the system. At the MSRC-BSC joint research center we are looking at how to support these facilities in the context of modern multi-core processors: How can we adapt processors so that they are better suited to modern safe programming languages? What is the right division of responsibility between what is done in hardware, and what is done in software? What are the impacts on the performance of the resulting systems?
In this talk I'll introduce our work on concurrency control, garbage collection, and work-stealing systems, and show how a small number of new features in a processor can support a wide variety of language runtime system facilities. I'll describe some of our initial results, and highlight some of the areas where research on formal semantics and verification carried out at Koc University will be valuable.
Tim Harris is a researcher at MSR Cambridge where he works on abstractions for using multi-core computers. He is currently working on the Barrelfish operating system, and on architecture support for programming language runtime systems. His other recent work has focused on the implementation of software transactional memory for multi-core computers, and the design of programming language features based on it.
Tim has a BA and PhD in computer science from Cambridge University Computer Laboratory. He was on the faculty at the Computer Laboratory from 2000-2004 where he led the department's research on concurrent data structures and contributed to the Xen virtual machine monitor project. He joined Microsoft Research in 2004.
He currently serves as vice-chair of EuroSys, the SIGOPS European
Chapter. He is general chair for ASPLOS 2012 in London, UK and serves
on the steering committee for TRANSACT. He has served on the program committees
of and as a reviewer for numerous conferences and journals.